1. Field of Use
The present invention relates to memories for the storage of program instructions and data in a computer system, and, more particularly, to a memory array selection mechanism which provides a processor access to multiple memory arrays. The total number of addressable locations in the memory arrays can exceed the number of unique memory addresses which can be generated by the processor. In addition, the processor may fetch program instructions from one memory array and associated data from another memory array.
2. Prior Art
In general, computer processors generate memory addresses of a fixed length. These addresses are used to access individual storage locations in the computer memory either for program instructions or for data. Most computer systems have a single memory array limited in size to a number of individual storage locations corresponding to the number of unique addresses which can be generated by the processor.
In order to expand the amount of memory locations available for use by the processor, some systems have employed separate memories for instructions and data. This is accomplished, for example, by appending to the memory address an instruction fetch signal generated in the processor. This technique expands the total memory space, but it requires the explicit generation of the processor instruction fetch signal at the processor/memory interface. Moreover, the distinction between memory for instructions and memory for data causes a loss of generality in the use of memory, which precludes applications in which either of the two memory spaces is insufficient, even if the total memory required is less than the total available.
Other systems have employed additional memory array selection registers in the processor. This expands the total memory by permitting memory selection among several memory arrays. However, this arrangement may not allow instructions in one array to access data in another array. In addition, this technique cannot be used with an existing processor without significant processor redesign, including the addition of one or more registers and the associated instructions to control them.